Consider the following 8085 assembly program | Consider the following set of 8085 instructions : MVI  – A, 8EH ADI  – 73 H JC  – DSPLY OUT – PORT1 HLT

Consider the following 8085 assembly program | Consider the following set of 8085 instructions : MVI  – A, 8EH ADI  – 73 H JC  – DSPLY OUT – PORT1 HLT

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Consider the following set of 8085 instructions : MVI  – A, 8EH ADI  – 73 H JC  – DSPLY OUT – PORT1 HLT Consider the following 8085 assembly program ?

  1. An 8085 uP executes the following instructions

2710 LXIH, 30 A0H

2710 LXIH , 30A0H

2713 DAD H

2714 PCHL

All addresses and contents are in hex. let PC be the contents of the program counter and HL be contents of the HL register pair just after executing PCHL. Which of the following statement is correct?

  • PC = 2715 H (b) PC = 30A0H

HL = 30A0H                      HL = 2715H

( C) PC = 6140 H        (D) PC = 6140H

HL = 6140H                    HL = 2715H

  1. Consider the following assembly language programs :

MVI    –  B,87H

MOV   – A,B

START :     JMP  – NEXT

MVI  – B,00H

XRA  –   B

OUT  – PORT2

HL

NEXT :       XRA  – B

JP   – START

OUT – PORT2

HLT

The execution of the above program in an 8085 microprocessor or will result in

  • An output of 87H at PORT1
  • An output of 87H at PORT2
  • Infinite looping of the program execution with accumulator data alternating between 00H and 87H
  • Infinite looping of the program execution with accumulator data alternating between 00H and 87H
  1. Consider the sequence of 8085 instruction given below LXI, H, 9258, MOV A, M CMA MOV M,A Which one of the following is performed by this sequence?
  • Contents of location 9258 are moved to the accumulator
  • Contents of location 9258 are compared with the contents of the accumulator
  • Contents of location 8529 are complemented and stored in location 8529
  • Contents of location 5892 are complemented and stored in location 5892
  1. In 8085, if the clock frequency is 5 MHz, the time required to execute an instruction of 18 T-states is
  • 0
  • 6
  • 0
  • 0
  1. Which one of the following is not a vectored interrupt?
  • TRAP
  • INTR
  • RST 3
  • RST 7.5
  1. Match list I (pre-terminals) with list II (applications) and select the correct answer using the codes given below the lists.

List  II              List II

  1. SID, SOD Wait state
  2. Ready Interrupt
  3. TRAP Serial data transfer
  4. ALE Memory or I/O read/write
  5. Address latch control

Codes

A      B      C     D

  • 3        1      5     2
  • 3        1       2     5
  • 4        3       2     5
  • 4        3       1     2
  1. In an 8085 microprocessor, the instruction CMP B has been executed while the content of the accumulator is less than that of register B. As a result
  • Carry flag will be set but zero flag will be reset
  • Carry flag will be reset but zero flag will be reset
  • Both carry flag and zero flag will be reset
  • Both carry flag and zero flag will be set
  1. It is desired to multiply the numbers 0AH by 0BH and store the result in the accumulator. The numbers are available in registers B and C respectively. A part of the 8085 program for this purpose is given below.

MVI A, 00H

LOOP, …………

……………..

……………..

HLT ………

END ……….

The sequence of instruction to complete the program would be

  • JNZ LOOP, ADD B, DCR C
  • ADD B, JNZ LOOP, ADD B
  • DCR C, JNZ LOOP, ADD B
  • ADD B, DCR C, JNZ LOOP
  1. After an arithmetic operation the flag register of 8085 up has the following contents :
D7 D6 D5 D4 D3 D2 D1 D0
1 0 X 1 X 0 X 1

 

The contents of accumulator after operation may by

  • 75
  • 6C
  • DB
  • B6
  1. Consider the following instruction:

MVI  A, A9H

MVI  B,57H

ADD B

ORA  A

The flag status (S,Z,CY) after the instruction ORA A is executed is

  • (0,1,1)
  • (0,1,0)
  • (1,0,0)
  • (1,0,1)
  1. Following is the statement of a 8085 assembly language program

LXI SP, EFFF H

CALL 3000 H

3000 H:  LXI H, 3CF4 H

PUSH PSW

SPHL

POP PSW

RET

On completion of RET execution, the content of SP is

  • 3CF0 H
  • 3CFB H
  • 3FFD H
  • EFFF H
  1. Consider the following set of 8085 instructions :

MVI  – A, 8EH

ADI  – 73 H

JC  – DSPLY

OUT – PORT1

HLT

DSPLY : XRA  – A

OUT – PORT1

HLT

The output at PORT1 is

  • 00
  • FEH
  • 01H
  • 11H
  1. Consider the following 8085 assembly program :

MVI – A, DATA1

MOV – B,A

SUI – 51H

MOV – A,B

SUI – 82H

JC – DSPLY

DLT:  XRA  – A

OUT – PORT1

HLT

DLT : MOV – A,B

OUT – PORT2

HLT

This program will display

  • The bytes from 51H to 82H at PORT2
  • 00H AT PORT1
  • All bytes at PORT1
  • The bytes from 52H to 81H at PORT2
  1. In an 8085 microprocessor system with memory mapped input
  • Input devices have 16-bit addresses
  • Input devices are accessed using in and out instructions
  • There can be a maximum of 256 input devices and 256 output devices
  • Arithmetic and logic operations can be directly performed with the input data
  1. In a microprocessor, the register which holds the address of the next instruction to befetched is
  • Accumulator
  • Program counter
  • Stack pointer
  • Instruction registers
  1. In a microprocessor, WAIT states are used to
  • Make the processor WAIT during a DMA operation
  • Make the processor WAIT during an interrupt processing
  • Make the processor WAIT during a power shunt down
  • Interface slow peripherals to the processor
  1. It is desired to mask is the high order bits (D7 – D4) of the data bytes in register C. consider the following set of instruction :

(P)      MOV – A,C

ANI  – F0H

MOV – C,A

HLT

(Q)       MOV – A,C

MVI – B,F0H

ANA  – B

MOV – C,A

HLT

( R)     MOV – A,C

MVI   – B,0FH

ANA – B

MOV – C,A

HLT

(S)      MOV – A,C

ANI – 0FH

MOV – C,A

HLT

The instruction set (s), which execute(s) the desired operation is/are

  • P and Q
  • R and S
  • Only P
  • Only S
  1. Consider the following 8085 instruction :

XRA  – A

MVI – B,4AH

SUI – 4FH

ANA – B

HLT

The contents of registers A and B are, respectively

  • 05, 4A
  • 4F,00
  • B1,4A
  • None of these
  1. When a CPU is interrupted, it
  • Stops execution of instructions
  • Acknowledge interrupt and branches subroutines
  • Acknowledge interrupt and continues
  • Acknowledge interrupt and waits for the next instruction from the interrupting device
  1. Consider the following 8085 assembly program :

MVI  – B,89H

MOV  – A,B

MOV – C,A

MVI – D,37H

OUT – PORT1

HLT

The output at PORT1 is

  • 89
  • 37
  • 00
  • None of these

Answers with Solutions

  1. ( C) 2710H LXI H, 30A0H : Load 16-bit data 30A0 in

2713H  DAD H        : 6140 H – HL

2714H  PCHL         copy the contents of 6140H of HL in PC

Thus, after execution above instruction, contents of PC and HL are same and that is 6140H.

  1. (B) step 1 : B = 87

Step 2 : A = 87 and B = 87

Step 3 : Control will jump at next

Step 4 : A = 10000111

B = 10000111

A = 000 00000 = 00 H

Step 5 : A = 00 H, that means Z = 0 (positive)

Contro1 jump at start.

Step 6 : Contro1 jump at next

Step 7 : A = 0000

B = 1000 0111

A = 1000 0111 = 87 H

MSB = 1,that means,Z = 1 (negative)

So, control will not jump.

Step 8 : At PORT 2, 87 H will available.

  1. (C ) step 1 : H = 92 and L = 58

Step 2 : A = content at memory add 9258

Step 3 : A – A

Step 4 : content of A will store at memory location 9258.

  1. (B) time required to execute an instruction is given by

T = 1/f x no. of T-states

= 1/5×106 x 18

  1. (B) vectored interrupts are those interrupts in which program controls transfer to a fixed location. In non-vectored interrupts, the location is not fixed. here, INTR is a non-vectored interrupt.
  2. (B) The 8085 has two signals to implement serial data transfer these are serial input data (SID) and serial output data (SOD).

Ready pin is used to delay the read or write cycle. When ready signal goes low, the microprocessor waits for an integral number of clock cycles.

TRAP is an interrupt signal.

ALE used for Address latch enable.

  1. (A) CMP B

Subtract the content of register B with accumulator.

As [ACC] < [B]

Given, CY = 1

After execution as

[ACC] = 0

Zero = 0

If A > B, carry flag is set and zero flag is reset.

  1. (D) to perform the multiplication of OA and OB stored at B and C, the program requires addition of content of B to accumulator to C times.

MVI A, 00H – Clear accumulator

Loop : ADD B – [B] + [A] – [A]

DCR C  – Decrement C

JNZ, LOOP – If C is not zero, jump to loop

HLT

END

  1. (D) The bit positions in flag register are as follows

 

D7 D6 D5 D4 D3 D2 D1 D0
S Z X AC X P X CY

 

S = 1, P = 0

Result must have odd parity and D7  = 1.

  1. (B) The ORA A instructions reset the CY flags.

S       Z     CY

X        x       x

MVI – A, A9H         x        x       x

MVI – B, 57H          x        x       x

ADD – B                  0        1      1

ORA                        0         1      0

  1. (B) LXISP, EFFF H; Load SP with data EFFH

CALL 3000 H ; jump to location 3000H

:

:

:

:

3000H   LXIH, 3CF4 ; Load HL with data 3CF4H

PUSH PSW ; Store contents of PSW to stack

: Copy contents of HL to

SP (3CF4H)

POP PSW  ; Restore contents of PSW from stack

RET ; stop

Before instruction SPHL the content of SP is 3CF4H.

After execution of POP PSW, SP + 2 – SP

After execution of RET, SP + 2 – SP

Thus, the contents of SP will be 3 CF4H + 4 = 3CF8H.

  1. (A) MVI – A,8EH ;8EH – A

ADI – 73H ;8EH + 73H – A = 01H

; CY = 1

JC   –  DSPLY : CY = 1, jump on DSPLY

OUT – PORT1

HLT

DSPLY : XRA     A              Clear A

OUT     PORTI     00 – PORTI

OUT     PORTI     00 – PORTI

  1. (A) MVI       A, DATA1  ; DATA 1 – A

MOV       B,A        ; A – B

SUI           51H       ; A – 51 H – A

JC           DLT      ; If CY = 1, jump on dlt

MOV       A,B      ; B – A

SUI         82H     ; A – 82 H – A

JU           DSPLY  ; IF CY = 1, jump on DSPLY

DLT :            XRA        A            ;  Clear A

OUT      PORT1   ; A – PORT1

DSPLY :        MOV     A,B        :   B – A

OUT     PORT2    ; A – PORT 2

HLT

If DATA1 is less 51H, SUI 51H Will set the CY flag and execution will jump on DLT. After this A will be cleared and output at PORT1 will be 00. If DATA1 is greater than 51H and less than or equal to 82H, execution will jump on DSPLY and DATA1 will be displayed at PORT2.

  1. (B,C)
  2. (B) Program counter holds the address of the next instruction to be fetched.
  3. (a) to make the processor wait during a DMA operation.
  4. (b) instruction set P and Q mask the lower order bits, not high order bits.

ANI   0FH  ; A AND 0FH – A

ANA    B    ; A AND B – A

  1. (D) XRA   A        ; Clear A

MVI    B,4AH  ; 4A – B

SUI    4FH       ; A – 4FH – A = B1H

ANA   B            ; A AND B – A = 00

HLT

A = 00, B = 4A

  1. (B) When an interrupt is acknowledged, CPU performs following steps :
  • CPU saves the PC contents on the stack.
  • It jumps to a vector location according to interrupt.
  1. (A) MVI B,89H  ; 89 – B

MOV    A,B       ; B – A

MOV   C,A       ; A – C

MVI     D,37 H  ; 37 – D

OUT   PORT1  ; Display A

The content of A is 89H.

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